Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric

ABSTRACT

A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.

FIELD OF THE INVENTION

[0001] The present invention relates to a method of forming asemiconductor memory array of floating gate memory cells. The presentinvention also relates to a semiconductor memory array of floating gatememory cells of the foregoing type.

BACKGROUND OF THE INVENTION

[0002] Non-volatile semiconductor memory cells using a floating gate tostore charges thereon and arrays of such non-volatile memory cellsformed in a semiconductor substrate are well known in the art.Typically, such floating gate memory cells have been of the split gatetype or stacked gate type. The memory cell utilizes a control gate thatis spaced apart and insulated from a floating gate. The control gate canfurther include a select gate portion. A layer of insulating material(e.g. oxide) is formed between the floating gate and control gate. Thethickness of this oxide layer is important because it dictates the levelof capacitive coupling between the two gates and it must be thin enoughto allow Fowler-Nordheim tunneling for those cells that are erased bytunneling electrons from the floating gate to the control gate.

[0003] Typically such memory cells are formed in an array configuration,with peripheral circuitry also formed on the same semiconductor die. Theperipheral circuitry often includes one or more high voltage MOStransistors for operating the memory cell array. FIG. 1 illustrates aconventional memory cell 1 from the memory cell area of the die, as wella conventional high voltage MOS transistor 2, all formed on the samesemiconductor die 3. The memory cell 1 is a split gate type memory cell.A tunneling oxide layer 4 is formed between the control gate CG and thefloating gate FG, with source S and drain D regions formed in thesubstrate. The transistor 2 includes a poly gate PG that is insulatedfrom the substrate 3 by a gate oxide 5, and overlaps with source S anddrain D, where the poly gate PG controls the conductivity of the channelregion between the source S and drain D.

[0004] Processing efficiency is important in the fabrication ofsemiconductor devices. Therefore, it is desirable to fabricatecorresponding memory and transistor elements using the same processingsteps. Thus, the memory cell control gates CG and the transistor polygates PG are preferably formed using the same polysilicon depositionstep. Likewise, the formation of the memory cell tunnel oxide 4 and thetransistor gate oxide 5 is formed using the same oxide formation step.

[0005]FIGS. 2A to 2D illustrate a conventional method of forming amemory cell in the memory cell area 6 of substrate 3, and a MOStransistor in the peripheral area 7 of substrate 3. Silicon dioxide(hereinafter “oxide”) layer 8, polysilicon (hereinafter “poly”) layer 9,and silicon nitride (hereinafter “nitride”) layer 10 are first formedover the substrate 3. A masking step is used to selectively etch andremove a portion of nitride layer 10, forming a hole 11 that exposes thepoly layer 9. The structure is oxidized to form oxide layer 12 over theexposed portion of poly layer 9 at the bottom of hole 11. The resultingstructure is shown in FIG. 2A.

[0006] Next, a series of etches are used to remove nitride layer 10, andthose portions of poly layer 9 and oxide layer 8 not protected by oxidelayer 12, as shown in FIG. 2B. Oxide layer 13 is then formed over thestructure, followed by the formation of nitride spacers 14, as shown inFIG. 2C. Finally, a poly deposition and masking step is used to formpoly block 15 on oxide layer 13 (laterally adjacent and vertically overpoly layer 9), and poly block 16 on oxide layer 13 (in peripheral area7). Ion implantation is used to form source regions 17 and drain regions18, as shown in FIG. 2D. Poly block 15 forms the memory cell controlgate, poly layer 9 forms the memory cell floating gate, and the portionof oxide layer 13 therebetween forms the memory cell tunnel oxide. Polyblock 16 forms the transistor poly gate, and the portion of oxide layer13 underneath poly block 16 forms the gate oxide for the transistor.

[0007] This fabrication process illustrates how the oxide layer 13serves as both the tunnel oxide for the memory cell 1 and the gate oxidefor the transistor 2. Thus, the thickness of the tunnel and gate oxidesis necessarily the same. However, this is not ideal for devices in whichthe MOS transistor 2 operates at a higher voltage than does the memorycell 1.

SUMMARY OF THE INVENTION

[0008] The present invention solves the aforementioned problem byproviding memory cells and MOS transistors on the same siliconsubstrate, wherein the same oxide layer forms the gate and tunneloxides, yet the MOS transistor gate oxide thickness is greater than thethickness of the memory cell tunnel oxide.

[0009] The present invention is an electrically programmable anderasable memory device that includes a substrate of semiconductormaterial having a memory area and a peripheral area, a memory cellformed in the memory area of the substrate, and a MOS transistor formedin the peripheral area of the substrate. The memory cell includes anelectrically conductive floating gate disposed over and insulated fromthe substrate, an electrically conductive control gate disposed adjacentto the floating gate, and an insulating layer formed in the memory andperipheral areas that includes a first portion that is disposed betweenthe control gate and the floating gate with a thickness permittingFowler-Nordheim tunneling of charges therethrough. The MOS transistorincludes an electrically conductive poly gate disposed over andinsulated from the substrate, and a second portion of the insulatinglayer being disposed between the poly gate and the substrate and havinga thickness that is greater than that of the first portion of theinsulating layer. The first and second portions of the insulating layerare initially formed as a continuous layer of material.

[0010] In another aspect of the present invention, the electricallyprogrammable and erasable memory device includes a substrate ofsemiconductor material that includes a memory area and a peripheralarea, a memory cell formed in the memory area of the substrate, and aMOS transistor formed in the peripheral area of the substrate. Thememory cell includes a first source region and a first drain regionformed in the substrate with a first channel region therebetween, anelectrically conductive floating gate disposed over and insulated fromat least a portion of the first channel region, an electricallyconductive control gate disposed adjacent to the floating gate, and aninsulating layer formed in the memory and peripheral areas, wherein theinsulating layer has a first portion that is disposed between thecontrol gate and the floating gate with a thickness permittingFowler-Nordheim tunneling of charges therethrough. The MOS transistorincludes a second source region and a second drain region formed in thesubstrate with a second channel region therebetween, an electricallyconductive poly gate disposed over and insulated from at least a portionof the second channel region, and a second portion of the insulatinglayer being disposed between the poly gate and the second channelregion, wherein the second portion of the insulating layer has athickness that is greater than that of the first portion of theinsulating layer. The first and second portions of the insulating layerare initially formed as a continuous layer of material.

[0011] In yet another aspect of the present invention, a method ofmaking an electrically programmable and erasable memory device includesthe steps of forming an electrically conductive floating gate disposedover and insulated from a memory area of a substrate, forming aninsulating layer that has a first portion formed over the memory area ofthe substrate and a second portion formed over a peripheral area of thesubstrate, wherein the insulating layer first portion has a thicknesspermitting Fowler-Nordheim tunneling of charges therethrough, changing athickness of one of the insulating layer first and second portionsrelative to the other of the insulating layer first and second portions,forming an electrically conductive control gate disposed adjacent to thefloating gate and insulated therefrom by the first portion of theinsulating layer, and forming an electrically conductive poly gatedisposed over the peripheral area of the substrate and insulatedtherefrom by the second portion of the insulating layer.

[0012] In yet one more aspect of the present invention, the method offorming an electrically programmable and erasable memory device includesthe steps of forming a memory cell in a memory area of a substrate, andforming an MOS transistor in a peripheral area of the substrate. Thememory cell formation includes the steps of forming a floating gate overand insulated from the substrate, and forming a control gate adjacent toand insulated from the floating gate. The MOS transistor formationincludes forming a poly gate over and insulated from the substrate. Theformation of the memory cell and the formation of the MOS transistortogether include the step of forming an insulating layer having a firstportion that is disposed between the control gate and the floating gatewith a thickness permitting Fowler-Nordheim tunneling of chargestherethrough, and a second portion that is disposed between the polygate and the substrate, wherein the second portion of the insulatinglayer has a thickness that is greater than that of the first portion ofthe insulating layer.

[0013] Other objects and features of the present invention will becomeapparent by a review of the specification, claims and appended figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross sectional view of a conventional memory cell andrelated peripheral MOS transistor.

[0015] FIGS. 2A-2D are cross sectional views of a conventionalsemiconductor structure showing in sequence the steps in the processingof the semiconductor structure in the formation of the conventionalmemory cell and peripheral MOS transistor of FIG. 1.

[0016] FIGS. 3A-3G are cross sectional views of a semiconductorstructure showing in sequence the steps in the processing of thesemiconductor structure in the formation of the memory cell andperipheral MOS transistor of the present invention.

[0017] FIGS. 4A-4C are cross sectional views of a semiconductorstructure showing in sequence the steps in an alternate embodiment ofthe processing of the semiconductor structure shown in FIG. 3C.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The method of the present invention is illustrated in FIGS.3A-3G, and begins with a semiconductor substrate 30, which is preferablyof P type and is well known in the art. The thicknesses of the layersdescribed below will depend upon the design rules and the processtechnology generation. It will be understood by those skilled in the artthat the present invention is not limited to any specific processtechnology generation, nor to any specific value in any of the processparameters described hereinafter. In addition, the following methoddescription focuses on the formation of a single memory cell and asingle MOS transistor, when in fact an array of such memory cells issimultaneously formed in a memory cell area 32 of the substrate 30, anda plurality of such transistors can be simultaneously formed in aperipheral area 34 of the substrate 30. Preferably, such memory cellsare formed in columns of active regions that are separated by columns ofinsulation areas, the formation of which is well known in the art.

[0019] As shown in FIG. 3A, a thin layer of insulation material 36, suchas oxide having a thickness approximately ˜50-150 Å, is formed onsubstrate 30 by any well known technique such as oxidation or deposition(e.g. chemical vapor deposition or CVD). A layer of conductive material38, such as polysilicon having a thickness of approximately ˜500-2000 Åis deposited on top of the oxide layer 36 by any well known process suchas Low Pressure CVD or LPCVD. Poly layer 38 may be doped by ionimplantation. Another layer of insulation material 40, such as nitridehaving a thickness of approximately ˜300-500 Å, is deposited over thepoly layer 38, preferably by CVD. Layers 36/38/40 are formed in both thememory cell area 32 and the peripheral area 34 of the semiconductorsubstrate 30. Next, a conventional photo-lithography scheme is used toform semi-recessed holes or trenches 42 in the structure in thefollowing manner. A suitable photo-resistant material is applied on thenitride layer 40 and a masking step is performed to selectively removethe photo-resistant material from a selected area. Where thephoto-resist material is removed, the exposed portion of nitride layer40 is removed using a standard nitride etch process (e.g. anisotropicnitride etch), leaving a hole or trench 42 that exposes the poly layer38. The structure is further processed to remove the remaining photoresist. A thermal oxidation process is used to oxidize the exposedportion of poly layer 38 in hole 42, to form a lens-shaped oxide layer44 over the exposed portion of poly layer 38, as shown in FIG. 3A.

[0020] Next, a nitride etch process is used to remove the remainingportions of nitride layer 40. This is followed by anisotropic poly andoxide etch steps to remove those portions of poly layer 38 and oxidelayer 36 that are not protected by oxide layer 44. The resultingstructure is shown in FIG. 3B.

[0021] Oxide layer 46 is formed over the structure, preferably using acombination of a high temperature oxide deposition process (HTO) with athickness of approximately 100-200 Å, and a thermal oxidation processwith a thickness of 10-50 Å. A layer of nitride 48 is formed over theoxide layer 46, having a thickness of approximately ˜100-300 Å. This isfollowed by the formation of photo resist material over the structure,and then a masking step in which the photo resist material is removedfrom the peripheral area 34 only, leaving a layer of photo resistmaterial 50 over the memory cell area 32, as shown in FIG. 3C.

[0022] A nitride etch process is used to remove the nitride layer 48from the peripheral area 34, while nitride layer 48 in the memory cellarea 32 (protected by photo resist 50) remains intact. The photo resist50 is then removed to result in the structure shown in FIG. 3D.

[0023] A thermal oxidation is next used to thicken oxide layer 46 in theperipheral area 34, but not in the memory cell area 32. Nitride layer 48in the memory cell area 32 acts as a mask so that the thermal oxidationprocess only grows thicker the exposed portion of oxide layer 46 in theperipheral area 34. The resulting structure is shown in FIG. 3E.

[0024] An anisotropic nitride etch is used to remove nitride layer 48,except for nitride spacers 52 formed on either side of the raisedportion (over oxide layer 44) of oxide layer 46, as shown in FIG. 3F.Polysilicon is deposited on oxide layer 46, and a masking step is usedto remove selected portions of the deposited polysilicon, except forpoly block 54 in the memory area 32 and for poly block 56 in theperipheral area 34. In the embodiment shown in FIG. 3G, the poly block54 has a first portion disposed laterally adjacent to poly layer 38, anda second portion disposed vertically over poly layer 38, with oxidelayer 46 disposed between poly layer 38 and poly block 54. Conventionalion implantation is then made across the structure to form source anddrain regions 58 and 60 in the memory area 32 of the substrate 30, andsource and drain regions 62 and 64 in the peripheral area 34 of thesubstrate 30. The source and drain regions have a conductivity type thatis different from that of the substrate or substrate well in which theyare formed. In the preferred embodiment, the source and drain regionsare all N+ regions. The resulting structure is shown in FIG. 3G.

[0025] In the memory cell area 32, a channel region 66 is defined in thesubstrate between the source 58 and drain 60. Poly layer 38 forms thecell's floating gate, which is disposed over and insulated from a firstportion of the channel region 66 and a portion of the source region 58.Poly block 54 forms the cell's control gate, which includes a firstportion 54 a that is disposed over and insulated from a second portionof the channel region 66 and a portion of the drain 60, and is laterallyadjacent to and insulated from the floating gate 38. The control gate 54has a second portion 54 b that is disposed over (vertically adjacent to)and insulated from the floating gate 54. A notch 68 is formed in thecontrol gate 54 by the nitride spacer 52, which helps prevent reversetunneling back to the floating gate or to the substrate. Thenon-volatile memory cell is of the split gate type as described in U.S.Pat. No. 5,572,054, which discloses the operation of such a non-volatilememory cell and an array formed thereby, and is hereby incorporatedherein by reference.

[0026] In the peripheral area 34, a channel region 70 is defined in thesubstrate between the source 62 and drain 64. Poly block 56 forms thetransistor cell's poly gate, which is disposed over and insulated fromthe channel region 70.

[0027] Oxide layer 46 has two separate portions: a thinner portion 72formed in the memory cell area 32 of the substrate 30, and a thickerportion 74 formed in the peripheral area 34 of the substrate 30. Part ofthe thinner portion 72 of oxide layer 46 forms the tunnel oxide of thememory cell through which electrons tunnel for memory cell operation(e.g. erase operation). Part of the thicker portion 74 of the oxidelayer 46 forms the gate oxide of the MOS transistor which insulates thepoly gate 56 from the substrate 70. Because the gate oxide of the MOStransistor is formed on a thicker portion of oxide layer 46 than is thetunneling oxide of the memory cell, the MOS transistor can betteroperate at a higher voltage than that of the memory cell. In thepreferred embodiment, the control gate is raised to an erase voltage ofapproximately 7 to 15 volts, and the MOS transistor operates at 1 or 2volts above that erase voltage. This difference of 1-2 volts provides amargin for better reliability in the operation of the semiconductormemory device.

[0028] FIGS. 3A-3G show the formation of oxide layer 46 over both theperipheral area 34 and the memory cell area 32, and then thickening ofthe oxide layer 46 only in the peripheral area 34. Alternately, however,the thickness of the oxide layer 46 in the memory cell area can bereduced, resulting in the same relative thicknesses of oxide layer 46 inthe peripheral and memory cell areas 34/32. FIGS. 4A-4C illustrate analternate embodiment of the present invention, which essentiallyinvolves the same processing steps as previously described with respectto FIGS. 3A-3G, but with the following exceptions. This alternateembodiment begins with the same structure as shown in FIG. 3C, exceptthat the thickness of oxide layer 46 is greater, and the photo resist 50is formed over the peripheral area 34 instead of memory cell area 32, asshown in FIG. 4A.

[0029] The subsequent nitride etch process removes the nitride layer 48from the memory cell area 32, while nitride layer 48 in the peripheralarea 34 (protected by photo resist 50) remains intact. The photo resist50 is then removed to result in the structure shown in FIG. 4B.

[0030] An oxide etch process is then used to reduce the thickness ofoxide layer 46 in the memory cell area 34, but not in the peripheralarea 34. The nitride layer 48 in the peripheral area 34 acts as a maskso that the oxide etch process only removes the top exposed portion ofoxide layer 46 in the memory cell area 32. The resulting structure isshown in FIG. 4C, which is further process as described above withrespect to FIG. 3G. It should be noted that nitride layer 48 is optionalin this embodiment, and that a nitride deposition and removal step canbe used to add the nitride spacer 52 to prevent reverse tunneling backto the floating gate or to the substrate in the finished memory cell.

[0031] It is to be understood that the present invention is not limitedto the embodiment described above and illustrated herein, butencompasses any and all variations falling within the scope of theappended claims. For example, the invention is disclosed in the contextof a split gate memory device, but it is also applicable to any memorycell design that includes a tunneling oxide between two conductiveelements, where the tunneling oxide layer extends to the substrate'speripheral area to form the gate oxide of a MOS transistor. Further,although the foregoing method describes the use of appropriately dopedpolysilicon as the conductive material used to form the memory cells, itshould be clear to those having ordinary skill in the art that anyappropriate conductive material can be used. In addition, anyappropriate insulator can be used in place of silicon dioxide or siliconnitride. Moreover, any appropriate material whose etch property differsfrom silicon dioxide (or any insulator) and from polysilicon (or anyconductor) can be used in place of silicon nitride. Further, as isapparent from the claims, not all method steps need be performed in theexact order illustrated or recited in the claims, but rather can beperformed in any order that allows the proper formation of the memorycell and MOS transistor of the present invention. Finally, while oxidelayer 46 is formed over the both the peripheral and memory cell areas34/32 as a single layer of material, this oxide layer could in fact beformed of multiple layers of insulating material, and could later bemade discontinuous by the formation of holes or trenches therein.

What is claimed is:
 1. An electrically programmable and erasable memorydevice comprising: a substrate of semiconductor material that includes amemory area and a peripheral area; a memory cell formed in the memoryarea of the substrate, wherein the memory cell includes: an electricallyconductive floating gate disposed over and insulated from the substrate,an electrically conductive control gate disposed adjacent to thefloating gate, and an insulating layer formed in the memory andperipheral areas that includes a first portion that is disposed betweenthe control gate and the floating gate with a thickness permittingFowler-Nordheim tunneling of charges therethrough; and an MOS transistorformed in the peripheral area of the substrate, wherein the MOStransistor includes: an electrically conductive poly gate disposed overand insulated from the substrate, and a second portion of the insulatinglayer being disposed between the poly gate and the substrate and havinga thickness that is greater than that of the first portion of theinsulating layer; wherein the first and second portions of theinsulating layer being initially formed as a continuous layer ofmaterial.
 2. The device of claim 1, wherein the memory cell furtherincludes: a first source region and a first drain region formed in thesubstrate, with a first channel region therebetween, wherein thefloating gate is disposed over and insulated from at least a portion ofthe first channel region.
 3. The device of claim 2, wherein the MOStransistor further includes: a second source region and a second drainregion formed in the substrate, with a second channel regiontherebetween, wherein the poly gate is disposed over and insulated fromat least a portion of the second channel region.
 4. The device of claim1, wherein the control gate has a first portion that is disposedlaterally adjacent to the floating gate.
 5. The device of claim 4,wherein the control gate first portion is disposed over a portion of thefirst channel region.
 6. The device of claim 5, wherein the control gatehas a second portion that is disposed over the floating gate.
 7. Thedevice of claim 1, wherein: the insulating layer second portion isformed directly on the peripheral area of the substrate, and the polygate is formed directly on the insulating layer second portion.
 8. Thedevice of claim 7, wherein the insulating layer first portion furtherextends between the substrate and the control gate.
 9. An electricallyprogrammable and erasable memory device comprising: a substrate ofsemiconductor material that includes a memory area and a peripheralarea; a memory cell formed in the memory area of the substrate, whereinthe memory cell includes: a first source region and a first drain regionformed in the substrate, with a first channel region therebetween, anelectrically conductive floating gate disposed over and insulated fromat least a portion of the first channel region, an electricallyconductive control gate disposed adjacent to the floating gate, and aninsulating layer formed in the memory and peripheral areas, wherein theinsulating layer has a first portion that is disposed between thecontrol gate and the floating gate with a thickness permittingFowler-Nordheim tunneling of charges therethrough; and an MOS transistorformed in the peripheral area of the substrate, wherein the MOStransistor includes: a second source region and a second drain regionformed in the substrate, with a second channel region therebetween, anelectrically conductive poly gate disposed over and insulated from atleast a portion of the second channel region, and a second portion ofthe insulating layer being disposed between the poly gate and the secondchannel region, wherein the second portion of the insulating layer has athickness that is greater than that of the first portion of theinsulating layer; wherein the first and second portions of theinsulating layer being initially formed as a continuous layer ofmaterial.
 10. The device of claim 9, wherein the control gate has afirst portion that is disposed laterally adjacent to the floating gate.11. The device of claim 10, wherein the control gate first portion isdisposed over a portion of the first channel region.
 12. The device ofclaim 11, wherein the control gate has a second portion that is disposedover the floating gate.
 13. The device of claim 9, wherein: theinsulating layer second portion is formed directly over the peripheralarea of the substrate, and the poly gate is formed directly over theinsulating layer second portion.
 14. The device of claim 13, wherein theinsulating layer first portion further extends between the substrate andthe control gate.
 15. A method of making an electrically programmableand erasable memory device, comprising the steps of: forming anelectrically conductive floating gate disposed over and insulated from amemory area of a substrate; forming an insulating layer that has a firstportion formed over the memory area of the substrate and a secondportion formed over a peripheral area of the substrate, wherein theinsulating layer first portion has a thickness permittingFowler-Nordheim tunneling of charges therethrough; changing a thicknessof one of the insulating layer first and second portions relative to theother of the insulating layer first and second portions; forming anelectrically conductive control gate disposed adjacent to the floatinggate and insulated therefrom by the first portion of the insulatinglayer; and forming an electrically conductive poly gate disposed overthe peripheral area of the substrate and insulated therefrom by thesecond portion of the insulating layer.
 16. The method of claim 15,further comprising the steps of: forming a first source region and afirst drain region in the substrate, with a first channel regiontherebetween, wherein the floating gate is disposed over and insulatedfrom at least a portion of the first channel region; and forming asecond source region and a second drain region in the substrate, with asecond channel region therebetween, wherein the poly gate is disposedover and insulated from at least a portion of the second channel region.17. The method of claim 15, wherein the formation of the control gateand the poly gate includes the steps of: depositing a layer ofconductive material over the insulating layer; and selectively removingportions of deposited conductive material except for a first portionthereof forming the control gate and a second portion thereof formingthe poly gate.
 18. The method of claim 15, wherein the changing of therelative thickness of the insulating layer first and second portionsincludes the steps of: forming a layer of material over the insulatinglayer; masking a first portion of the layer of material formed over thefirst portion of the insulating layer, wherein a second portion of thelayer of material formed over the second portion of the insulating layeris left unmasked; removing the unmasked second portion of the layer ofmaterial to expose the second portion of the insulating layer; andincreasing the thickness of the exposed second portion of the insulatinglayer.
 19. The method of claim 18 wherein the increasing of thethickness of the exposed insulating layer second portion includesthermally oxidizing the exposed insulating layer second portion.
 20. Themethod of claim 15, wherein the changing of the relative thickness ofthe insulating layer first and second portions includes the steps of:forming a layer of material over the insulating layer; masking a firstportion of the layer of material formed over the second portion of theinsulating layer, wherein a second portion of the layer of materialformed over the first portion of the insulating layer is left unmasked;removing the unmasked second portion of the layer of material to exposethe first portion of the insulating layer; and removing a top portion ofthe exposed first portion of the insulating layer.
 21. A method offorming an electrically programmable and erasable memory device,comprising the steps of: forming a memory cell in a memory area of asubstrate, wherein the memory cell formation includes the steps of:forming a floating gate over and insulated from the substrate, andforming a control gate adjacent to and insulated from the floating gate;forming an MOS transistor in a peripheral area of the substrate, whereinthe MOS transistor formation includes forming a poly gate over andinsulated from the substrate; wherein the formation of the memory celland the formation of the MOS transistor together include the step of:forming an insulating layer having a first portion that is disposedbetween the control gate and the floating gate with a thicknesspermitting Fowler-Nordheim tunneling of charges therethrough, and asecond portion that is disposed between the poly gate and the substrate,wherein the second portion of the insulating layer has a thickness thatis greater than that of the first portion of the insulating layer. 22.The method of claim 21, further comprising the steps of: forming firstsource and drain regions with a first channel region therebetween in thesubstrate, wherein the floating gate is disposed over at least a portionof the first channel region; and forming second source and drain regionswith a second channel region therebetween in the substrate, wherein thepoly gate is disposed over at least a portion of the second channelregion.
 23. The method of claim 21, wherein the formation of theinsulating layer includes the steps of: forming the first and secondportions of the insulating layer with a uniform thickness over thememory and peripheral areas of the substrate; and changing the thicknessof one of the insulating layer first and second portions relative to thethickness of the other of the insulating layer first and second portion.24. The method of claim 21, wherein the formation of the control gateand the poly gate includes the steps of: depositing a layer ofconductive material over the insulating layer; and selectively removingportions of deposited conductive material except for a first portionthereof forming the control gate and a second portion thereof formingthe poly gate.
 25. The method of claim 23, wherein the changing of therelative thickness of the insulating layer first and second portionsincludes the steps of: forming a layer of material over the insulatinglayer; masking a first portion of the layer of material formed over theinsulating layer first portion, wherein a second portion of the layer ofmaterial formed over the second portion of the insulating layer is leftunmasked; removing the unmasked second portion of the layer of materialto expose the insulating layer second portion; and increasing thethickness of the exposed second portion of the insulating layer.
 26. Themethod of claim 25 wherein the increasing of the thickness of theexposed insulating layer second portion includes thermally oxidizing theexposed insulating layer second portion.
 27. The method of claim 23,wherein the changing of the relative thickness of the insulating layerfirst and second portions includes the steps of: forming a layer ofmaterial over the insulating layer; masking a first portion of the layerof material formed over the second portion of the insulating layer,wherein a second portion of the layer of material formed over the firstportion of the insulating layer is left unmasked; removing the unmaskedsecond portion of the layer of material to expose the first portion ofthe insulating layer; and removing a top portion of the exposed firstportion of the insulating layer.